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    "# [Py4Hw User Guide](../UserGuide.ipynb) > 4.3 Clock Enable"
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    "Synchronous hardware design receives its name from the fact that typically there is a global clock that synchronizes all sequential elements of the circuit.\n",
    "\n",
    "Having a global synchronous clock is a very common circuit design technique that symplifies the work of timing analysis and reduces complex timing errors.\n",
    "\n",
    "However, modern circuits can have different parts with different clocking requirements, or, in many designs, it is very common that some part **stalls** (i.e. stops its activity) while waiting for an event.\n",
    "\n",
    "There are some options to stop the activity of a sequential circuit.\n",
    "One of the easiest is to stop its clock signal. This is called **clock gating**.\n",
    "\n",
    "However, clock gating increases the complexity of timing analysis and it is generally not recommended in synchronous design.\n",
    "\n",
    "An alternative is **clock enabling**.\n",
    "\n",
    "We basically need an **clk_enable** signal in sequential blocks."
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    "## <span style=\"color:red\"> INFO </span>\n",
    "**py4hw** recommends you to use the port name **clk_enable** for clock enable ports in sequential circuits. This could be used by some future tools of the framework. "
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